Bcd to binary converter

ABSTRACT

Where Nbcd is the binary coded decimal number, i is the maximum decimal order of the decimal number, and b is the binary coded decimal signal and has a logic value of 1 or 0.   A high-speed binary coded decimal to binary converter having a plurality of full adders and half adders arranged to add the binary coded decimal signals to provide the binary signals in accordance with the following equation:

United States Patent Mersten 5] Mar. 14, 1972 BCD TO BINARY CONVERTER Primary Examiner-Maynard R. Wilbur Assistant ExaminerJoseph M. 'lhesz, Jr.

[72] Inventor: Gerald S. Mersten, Caldwell, NJ. Att0mey Rona]d G. Gillespie and name, Arms, Hm, [73] Assignee: The Bendix Corporation Smith n Thompson [22] Filed: Aug. 29, 1969 57] ABSTRACT [21 1 PP 854,078 A high-speed binary coded decimal to binary converter having a plurality of full adders and half adders arranged to add the binary coded decimal signals to provide the binary signals in 5?} gf' kffffff '""""""""'fffffjffffiiffg% 492%!92?EEMHQ QJQWEHsHR 9P= V A [58] Field of Search ..235/155, 92; 340/347 DD (bj z 2 1, 2 2 10 References b 2 [I 2 b 2") X 10 UNITED STATES PATENTS ["222 1M2) X (1 h N th ['3' Oddd al ber,"sthemax- 3,170,062 2/1965 Boese et al ..23s/15s z z g 'z f z f zgf g 'i L is the g gi et nary coded decimal signal and has a logic value of l or 0. a1 2,729,811 1/1956 Gloess SCIaims, l DrawingFigm-e 3,524,976 8/1970 THUMBWHEEL SWITCH 3;

HALF FULL ADDER l D C I4A LDDER l8 l4 s 5 S s TO BLNARY COMPUTER S S REGISTER BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to coded converters and, more particularly, to a binary coded decimal to binary converter.

2. Description of the Prior Art Heretofore, binary coded decimal to binary converters, such as the type disclosed in us. Pat. No. 3,276,013 issued Sept. 27, I966 to G. F. Chandler, requires a conversion time corresponding to the decimal value of the binary coded decimal signals. The Chandler converter counts timing pulses with a binary counter in accordance with the counting down of binary coded decimal counters to effect the conversion. The conversion time therefore corresponds to the value of the decimal number.

Other binary coded decimal to binary converters require a conversion time corresponding to the number of binary coded decimal signals to be converted.

The present invention provides high speed conversion of binary coded decimal signals to binary signals. The conversion time corresponds directly to the response time of the parts used. The present invention further distinguishes over the Chandler converter by using only adders to accomplish the conversion.

SUMMARY OF THE INVENTION A binary coded decimal to binary converter comprises a switch for providing binary signals b b b and b cor responding to each digit of a decimal number. A plurality of adders connected to the switch adds the binary signals in accordance with the decimal order i of each digit and provides an output corresponding to the addition. A register connected to the adders provides a binary signal corresponding to the decimal number in accordance with the outputs from the adders.

One object of the present invention is to provide a high speed binary coded decimal to binary converter.

Another object of the present invention is to provide a converter in which the time to convert binary coded decimal signals to binary signals increases only slightly for a large increase in the number of binary coded decimal signals to be converted.

Another object of the present invention is to provide a binary coded decimal to binary converter which continuously converts binary coded decimal signals.

Another object of the present invention is to provide a binary coded decimal to binary converter which does not require timing pulses or circuitry for controlling the application of binary coded decimal signals to the converter.

The foregoing and other objects and advantages of the invention will appear more fully hereinafter from a consideration of the detailed description which follows, taken together with the accompanying drawing wherein one embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawing is for illustration purposes only and is not to be construed as defining the limits of the invention.

DESCRIPTION OF THE DRAWING The drawing shows a novel binary coded decimal to binary converter constructed in accordance with the present inven-. tion, for converting a three digit decimal number to its equivalent binary signal.

DESCRIPTION OF THE INVENTION For purposes of illustration, Equation (1) of the abstract is 7 rewritten for a three digit decimal number as follows:

The powers of 10 multipliers may be rewritten in binary form so that Equation is now written as:

After performing the indicated multiplication, Equation (3) an t be WEE?! as.

l s e idl iibfisimeli kq arels Referring to the drawing, there is shown a decimal to binary ,converter having a thumbwheel switch 3 providing binary coded decimal signals b through b corresponding to a decimal number set in switch 3 by thumbwheels 5, 7 and 8. Switch 3 applies the binary coded decimal signals to a novel binary coded decimal to binary computer 9. Computer 9 includes conventional-type full adders 14 through 14M and con- 0 ventional-type half adders 18 through 18H arranged to add the binary signals from switch 3 to provide signals corresponding to different terms of Equation (5). Each full adder or half adder provides one output S corresponding to the sum and another output C corresponding to the carry. The signals from computer 9 are applied to a register 19 having 2 through 2 inputs.

' Binary signal b from switch 3 is applied directly to the 2 input of register 19 by computer 9. Full adder l4 adds signals b and b from switch 3 and provides a corresponding signal to the 2 input of register 19. Full adders 14A and 14B are connected together and to switch 3 to add signals b b,,' and b from switch 3. Full adder 148 applies a signal corresponding to the term (b -l-b +b of Equation (5) to the 2 input of register 19.

Full adders 14C, 14D and ME are serially connected together and to switch 3 to add signals b b b and b Full adder 14E provides a signal corresponding to the term (b b, +b, +b in Equation (5 to the 2 input or register 19.

A signal corresponding to the term (b +b +b in Equation (5) is applied to the 2 input of register 19 by full adder 146 which is connected to full adder 14F by half adder 18. Full adders 14F and are also connected to switch 3 to add signals b b and bzz.

Signals b b and b from switch 3 are added in accordance with the term (b, +b +b of Equation 5 by full adders MR and 14]. Full adder 14H and half adder 18A are connected to switch 3. Full adder 141 is connected to full adder 14H and to half adder 18A by half adder 18B to provide a signal corresponding to the addition to the 2 input of register 19.

The 2 input of register 19 receives a signal from a full adder 14K corresponding to the term (b, +b +b of Equation (5). Full adder 14] applies a signal corresponding to the sum of signals 11 and b received from switch 3 to full adder 14K. Half adder 18C applies signal b from switch 3 through half adder 18D to full adder 14K.

Full adder 14L adds signals b and b from switch 3 and applies a signal corresponding to the term (b,,+b of Equation 5 through half adder 18E to the 2 input of register 19. Full adder 14M adds signals b and b from switch 3 and applies a signal corresponding to the term (b +b of Equation (5) through half adder 18F to the 2 input of register 19. Half adders 180 and 18H add binary signal b with carry signals from full adder 14M and halfadder 18F, respectively. Halfadder 18 applies a signal corresponding to the term 11 of Equation (5) to 2 input of register 19.

Full adders 14, 14A, 14D and half adders 18, 18B and 18D are serially connected to provide for the carry function of their operation. For a similar reason, full adders 14C and 14F and half adders 18A and 18C are serially connected. Full adders 14H, 14], 14L and 14M and half adder 180 are serially connected to provide for the carry function. Similarly, full adders 14B, ME, 146, 14] and 14K and half adders 18E, 18F and 18H are serially connected to provide for the carry function.

A source 20 applies a shift pulse train E,, on a periodic basis to register 19 to shift out the content as a serial binary signal. When parallel binary signals are desired, register 19 and source 20 may be omitted, and the signals from computer 9 may be used directly.

The following tables show the logic states of the different inputs and outputs of the indicated elements during the operation of the present invention while converting, for purpose of illustration, decimal number 343 to a binary signal corresponding to the binary number 0101010111.

Switch 3 binary coded decimal signals a b 2 u m lfl 0: ar n 0 0 l l 0 l 0 0 0 0 l l Full adder outputs 14 14A 14B 14C MD ME 14F S C S C S C S C S C S C S C l 0 0 0 l 0 I 0 l 0 0 l l 0 MG l4H [4i [4] 14K 14L l4M S C S C S C S C SC C S C l 0 l 0 0 l 0 l 1 0 0 l l 0 Half adder outputs l8 [8A 18B lSC 18D 18E 18F 18G 18H S C S C S C S C S C S C S C S S l 0 l 0 l 0 0 0 0 0 0 0 l O 0 0 Inputs to register 2! 2K 27 2|! 2! 24 23 22 2! 0 l 0 l 0 l 0 l 1 l A binary coded decimal to binary converter as heretofore described is a high speed converter for which the conversion time increases only slightly for a large increase in the number of binary coded decimal signals to be converted. Furthermore, the aforementioned converter provides continuous conversion of the binary coded decimal signals and thus does not require control circuitry or timing pulses.

Although a binary coded decimal to binary converter for converting binary coded decimal signals corresponding to a three-digit decimal number has been shown, a decimal number having more or less digits may be converted by providing a converter in accordance with an equation derived from Equation l that is similar to Equation (5).

Although but a single embodiment of the invention has been illustrated and described in detail, it is to be expressly understood that the invention is not limited thereto. Various changes may also be made in the design and arrangement of the parts without departing from the spirit and scope of the invention as the same will now be understood by those skilled in the art.

What is claimed is:

1. A highspeed binary coded decimal to binary converter, comprising:

means for providing binary coded decimal signals b b b and b corresponding to each digit of a decimal number. where i is the decimal order of each digit and 0 to 3 are the decimal orders of each binary,

adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the following equation after the IQ multipliers are converted to binary form:

the adding means including a plurality of adders and half adders arranged to add the coefficients of each power of 2 and a carry signal from the adder of the next lower order of 2 and providing signals representing a coefficient of each power of 2 in the final binary number, said converter being constructed and arranged to operate in parallel fashion for high speed conversion, and

output means connected to the adding means for providing a binary signal corresponding to the decimal number in accordance with the outputs from the adding means. 2. A converter of the kind described in claim 1 in which the binary coded decimal signal means includes means for setting the decimal number, and means connected to the setting means for converting each digit in the decimal number to binary coded decimal signals.

3. A converter of the kind described in claim 1 in which the output means includes a register, connected to the adding means, for storing the binary number and providing the binary signal corresponding to the stored binary number.

4. A binary coded decimal to binary converter comprising: means for providing binary coded decimal signals 11, b b and b corresponding to each digit of a decimal number,

adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the decimal order 1' of each digit and providing outputs corresponding thereto,

output means connected to the adding means for providing a binary signal corresponding to the decimal number in accordance with the outputs from the adding means, the adding means including means for applying a binary coded signal [2 from the binary coded decimal signal means to the output means as a binary signal corresponding to 2 and including a plurality of serially connected adders connecting the binary coded decimal signal means to the output means and in which a first adder adds signals b and b to provide a binary carry signal and a binary signal corresponding to 2, a second adder adds signals 5 b an b and the carry signal from the first adder to provide a binary carry signal and a binary signal corresponding to 2 a third adder adds signals b b b and b and the carry signal from the second adder to provide a binary carry signal and a binary signal corresponding to 2", a fourth adder adds signals b b and b and the carry signal from the third adder to provide a carry signal and a binary signal corresponding to 2 a fifth adder adds signals b b and b and the carry signal from the fourth adder to provide a binary carry signal and a binary signal corresponding to 2 a sixth adder adds signals b bgo and b and the carry signal from the fifth adder to provide a binary carry signal and a binary signal corresponding to 2, a seventh adder adds signals b and b and the carry signal from the sixth adder to provide a binary carry signal and a binary signal corresponding to 2, and an eighth adder adds signals b and b and the carry signal from the seventh adder to provide a binary carry signal and a binary signal corresponding to 2 and a ninth adder adds signal b and the carry signal from the eighth adder to provide a signal corresponding to 2 5. A converter of the kind described in claim 4 in which the first adder is a first full adder, the second adder includes second and third full adders connected to the binary coded decimal signal means, and to each other, the third full adder being also connected to output means; the third adder includes fourth, fifth and sixth full adders connected to the binary coded decimal signal means and the fifth full adder also connects the fourth full adder to the sixth full adder which is also connected to the output means; the fourth adder includes seventh and eighth full adders connected to the binary coded decimal signal means and the eighth full adder is also connected to the output means, and a first half adder connecting the seventh and eighth full adders; the fifth adder includes a ninth full adder and a second half adder connected to the binary coded decimal signal means, a th full adder connected to the ninth full adder and to the output means and a third half adder connecting the second half adder to the 10th full adder; the sixth adder includes an 1 lth full adder and a fourth half adder connected to the binary coded decimal signal means, a 12th full adder connected to the 11th full adder and to the output means, and a fifth half adder connecting the fourth halt adder to the 12th full adder; the seventh adder includes a 13th full adder connected to the connecting means and a sixth half adder connecting the 13th full adder to the output means; the eighth adder includes a 14th full adder connected to the binary coded decimal signal means and a seventh half adder connecting the 14th full adder to the output means; and the ninth adder includes an eighth half adder connected to the binary coded decimal signal means and a ninth half adder connecting the eighth half adder to the output means.

i t k 

1. A high speed binary coded decimal to binary converter, comprising: means for providing binary coded decimal signals bi3, bi2, bi1 and bi0 corresponding to each digit of a decimal number, where i is the decimal order of each digit and 0 to 3 are the decimal orders of each binary, adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the following equation after the 10 multipliers are converted to binary form:
 2. A converter of the kind described in claim 1 in which the binary coded decimal signal means includes means for setting the decimal number, and means connected to the setting means for converting each digit in the decimal number to binary coded decimal signals.
 3. A converter of the kind described in claim 1 in which the output means includes a register, connected to the adding means, for storing the binary number and providing the binary signal corresponding to the stored binary number.
 4. A binary coded decimal to binary converter comprising: means for providing binary coded decimal signals bi3, bi2, bi1 and bi0 corresponding to each digit of a decimal number, adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the decimal order i of each digit and providing outputs corresponding thereto, output means connected to the adding means for providing a binary signal corresponding to the decimal number in accordance with the outputs from the adding means, the adding means including means for applying a binary coded decimal signal b00 from the binary coded decimal signal means to the output means as a binary signal corresponding to 20 and including a plurality of serially connected adders connecting the binary coded decimal signal means to the output means and in which a first adder adds signals b01 and b10 to provide a binary carry signal and a binary signal corresponding to 21, a second adder adds signals b02, b11 and b20 and the carry signal from the first adder to provide a binary carry signal and a binary signal corresponding to 22, a third adder adds signals b03, b10, b12 and b21 and the carry signal from the second adder to provide a binary carry signal and a binary signal corresponding to 23, a fourth adder adds signals b11, b13 and b22 and the carry signal from the third adder to provide a carry signal and a binary signal corresponding to 24, a fifth adder adds signaLs b12, b20 and b23 and the carry signal from the fourth adder to provide a binary carry signal and a binary signal corresponding to 25, a sixth adder adds signals b13, b20 and b21 and the carry signal from the fifth adder to provide a binary carry signal and a binary signal corresponding to 26, a seventh adder adds signals b21 and b22 and the carry signal from the sixth adder to provide a binary carry signal and a binary signal corresponding to 27, and an eighth adder adds signals b22 and b23 and the carry signal from the seventh adder to provide a binary carry signal and a binary signal corresponding to 28, and a ninth adder adds signal b23 and the carry signal from the eighth adder to provide a signal corresponding to
 29. 5. A converter of the kind described in claim 4 in which the first adder is a first full adder, the second adder includes second and third full adders connected to the binary coded decimal signal means, and to each other, the third full adder being also connected to output means; the third adder includes fourth, fifth and sixth full adders connected to the binary coded decimal signal means and the fifth full adder also connects the fourth full adder to the sixth full adder which is also connected to the output means; the fourth adder includes seventh and eighth full adders connected to the binary coded decimal signal means and the eighth full adder is also connected to the output means, and a first half adder connecting the seventh and eighth full adders; the fifth adder includes a ninth full adder and a second half adder connected to the binary coded decimal signal means, a 10th full adder connected to the ninth full adder and to the output means and a third half adder connecting the second half adder to the 10th full adder; the sixth adder includes an 11th full adder and a fourth half adder connected to the binary coded decimal signal means, a 12th full adder connected to the 11th full adder and to the output means, and a fifth half adder connecting the fourth half adder to the 12th full adder; the seventh adder includes a 13th full adder connected to the connecting means and a sixth half adder connecting the 13th full adder to the output means; the eighth adder includes a 14th full adder connected to the binary coded decimal signal means and a seventh half adder connecting the 14th full adder to the output means; and the ninth adder includes an eighth half adder connected to the binary coded decimal signal means and a ninth half adder connecting the eighth half adder to the output means. 